The present invention relates to a method and/or architecture for programmable logic devices generally and, more particularly, to a programmable logic device configuration port architecture and logic.
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-product(SOP) terms in response to the product terms, and a number of logic elements (i.e., macrocells) configured to generate a desired output in response to the sum-of-products terms. The sum-of-products terms can also be generated using programmable NOR-NOR logic.
The arrangement and operation of components within the PLD are programmed by architecture configuration bits. The architecture configuration bits are set prior to normal operation of a PLD. The bits are set using an operation called xe2x80x9cprogrammingxe2x80x9d or xe2x80x9cconfigurationxe2x80x9d. The configuration bits can be stored in volatile memory (i.e., SRAM) or non-volatile memory (i.e., EEPROM/flash). When the configuration bits are stored in volatile memory, the configuration bits need to be loaded from an off-chip non-volatile memory, a micro controller, or some other source.
The present invention concerns a programmable logic device (PLD) comprising a configuration controller. The configuration controller may be configured to (i) retrieve data and (ii) program a number of configuration bits of the PLD in response to the data.
The objects, features and advantages of the present invention include providing a programmable logic device configuration port architecture and logic that may (i)provide flexible configuration capabilities, (ii) use data compression,